1. Field of the Invention
The present invention relates to flash memory devices. More particularly, the present invention relates to a flash-based programmable logic device such as a field programmable gate array (“FPGA”) where a high write-to-erase threshold separation is required.
2. The Prior Art
Flash electrically erasable programmable read-only memory (EEPROM) systems are commonly used as non-volatile memories in many electronic devices, including programmable logic devices such as FPGAs. Although the term “flash” often refers to memories that are bulk erased on a page-by-page, sector-by-sector, or entire array basis, the term is generally used in the art to refer to any electrically erasable (and re-programmable) non-volatile memory technology, regardless of the particular erase scheme.
The most common flash memory devices are comprised of floating-gate transistors, though other flash technologies such as SONOS, nano-crystal, and other non-volatile transistors are also known. For floating gate transistors, there is a distribution of rates at which charge moves onto or off of the floating gate. This may be caused, for example, by slight physical variations in each transistor such as variations in tunnel oxide layers. As compared with most memory cell transistors in a particular memory array, transistors in which charge moves relatively quickly into and out of the floating gate are described as “fast,” and transistors in which charge moves relatively slowly into and out of the floating gate are described as “slow.” These fast and slow bits are commonly referred to as “tail” bits because they comprise the “tails” of a normal distribution of memory cell program and erase speed and are the first and last flash memory cells to program and erase. A “cell” refers to a unit or “bit” of memory that may be comprised of a single transistor, multiple transistors, or transistors with additional circuitry. A flash memory cell may be used to store data or to configure the logic or routing of a programmable logic device such as an FPGA.
In traditional flash memory systems and flash-based programmable logic devices using Fowler-Nordheim programming and erase, a memory cell is programmed with a single write pulse on the cell's row (word) line simultaneous with a single write pulse on the cell's column (bit) line, which are together sufficient to create a voltage differential across the device to move electrons through a tunnel oxide onto the floating gate (or equivalent structure). The voltage of each pulse is ramped from an initial value to a final value over the course of the pulse (see FIG. 1B). An erase operation is similarly performed with single column and row pulses that ramp from an initial voltage to a final voltage.
Due to manufacturing tolerances there is a distribution in the behavior of cells within an addressed word line. That is, the degree to which a non-volatile transistor cell is programmed or erased (the amount of charge on the floating gate of the transistor) is not completely uniform across transistors, but varies according to a distribution. The separation between the amount of charge on the “least erased” transistor and the amount of charge on the “least programmed” transistor is the “window” of the device. The larger the window, the easier it is to read whether a device is erased or programmed. If there is no window (i.e., the distribution of programmed and erased transistors overlaps), then the device will not operate correctly. In a flash-based FPGA, a wider write-erase window is required than in a standard flash memory because, rather than just storing information, FPGA cells perform logic operations. Therefore, FPGA cells must be either turned on hard enough to operate as low-resistance signal paths, or turned off hard enough that they reduce leakage during operation.
Programming of the non-volatile programmable cells in a flash-based programmable logic device is generally performed on a “row-by-row” basis. In one example, a row line or “wordline” is connected to the control gates of a row of non-volatile transistors in an array. When cells in a given row are to be programmed, a program voltage is applied to the row line in a pulse, as described above. Therefore, the control gates of all cells in the row receive the program voltage applied to the row line. Each cell in the row is also connected to a column line or “bitline.” For the cells to be programmed, a program voltage is applied to the column line of each cell to be programmed simultaneously with the application of the program voltage to the row line. As shown in FIG. 1B, the program voltages of the row and column lines are generally of opposite signs to create a large voltage differential across the cell.
While the non-volatile transistors selected for programming are being programmed, neighboring transistors may be affected by the large programming voltages applied in the vicinity, especially the voltage applied to the control gates of the unselected devices via the row lines. This is referred to as “disturb” and is illustrated in FIG. 1A.
FIG. 1A shows a graphic representation of the distribution of voltages for programmed and erased non-volatile memory cells. The distributions of FIG. 1A can be thought of to represent the voltages on the floating gates (or other charge-holding structures) of non-volatile transistors. It is not practical, however, to actually measure the voltage on a floating gate, so typically a proxy-measurement is used to develop the data represented in FIG. 1A. This proxy measurement may be, for example, a measurement of the control gate voltage needed to program or erase the cell, or the threshold voltage of a programmed or erased cell.
FIG. 1A shows a distribution of erased cell floating gate voltages 2 following a bulk erase of cells on a device. Following the bulk erase, selected cells in the device are programmed. The distribution of voltages on programmed cells is shown as curve 6. Curve 4 represents the voltages on erased devices that were not programmed following the bulk erase operation. Curve 4 is shifted from curve 2 due to the disturb effects of the programming operation. The effects of disturb, as illustrated in FIG. 1A, are to move the distribution of charges present on the erased devices closer to the distribution present on programmed devices. This leads to a narrower window 8 and, if disturb is high enough, could lead to errors on the device.
In order to partially reduce the disturb effect of the program voltage placed on the row line of a row containing cells being programmed, an inhibit voltage is placed on the column lines of the cells in the row that are not being programmed. The inhibit voltage is typically of opposite sign to the column line program voltage, and helps reduce the voltage differential across the cells that are not being programmed, thereby reducing disturb effects. The inhibit voltage is not sufficient, however, to eliminate disturb effects, or even to reduce them to acceptable levels in many cases.
Applying programming voltages to transistors to be programmed in a simple linear ramp, as shown in FIG. 1B results in the effects shown in FIG. 1A. The gate disturb induced on near-by transistors during the write pulse pushes the erased population towards the programmed population, narrowing the cell window. During the write pulse, since the program voltage is applied to an entire row, cells (“bits”) with different physical characteristics are selected. Fast bits tend to be programmed more quickly and slow bits need either longer or higher write voltages to meet the intended program level. Thus, for a single write pulse mode, the write pulse must be parameterized suitably to accommodate the slow-moving bits (i.e., to program the transistors most “resistant” to programming) in the program distribution. A programming method using a single pulse write mode cannot differentiate the row by row variation in device characteristics across the whole core area. It results in wider threshold distribution especially on the erase bit due to increasing the gate disturb on the erased population. Tighter erase bit distribution is especially important for a flash-based FPGA to have target switch performance.
Various programming schemes for enhancing the distribution of threshold values of programmed and erased cells in non-volatile memory devices are known in the art. For example, Intel Corporation of Santa Clara, Calif. has employed a convergence scheme for creating a tighter distribution of programmed cells on flash memory devices employing channel hot electron (“CHE”) program and erase. This method operates by applying a single low-voltage convergence pulse to programmed cells and then testing the devices to determine if the distribution of cell threshold voltages meets a predetermined standard.